Verilog-AMS in Gnucap

Gnucap is a free/libre versatile and modern, modular, analog and mixed-signal simulator. Verilog-AMS is a standardised behavioural language for analog and mixed-signal systems based on the IEEE 1364-2005 industry standard, commonly known as Verilog. Verilog and its extensions offer a portable representation for circuits and device models consistent across application domains. With funding from NLnet we are pushing for standardisation in an otherwise heterogeneous environment of traditional and incompatible tools.

We are working on a first open source (and free/libre) Verilog-AMS implementation. It consists of extensions for Gnucap that elaborate circuits represented in Verilog, provide suitable simulation algorithms and interface with artifacts from related projects. The companion tool Modelgen-Verilog deals with behavioural models for mixed-signal devices, turning them into plugins for Gnucap.

In this talk we will explain the need for standard support in free software tools and summarise the developments since FOSDEM-25. We have filled gaps in the simulator infrastructure and extended the standard coverage vastly improving the user experience. We will outline some related ongoing activities, e.g. on porting open source PDKs to Verilog, on the Qucs schematic editor and on device libraries as well as testing and QA.