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FOSDEM PWA

RISC-V had 40 years of history to learn from: What it gets right, and what it gets hilariously wrong

H.2214 | Day 1 | 11:20 - 11:55 | Speakers: FelixCLC

RISC-V had 40 years of history to learn from: What it gets right, and what it gets hilariously wrong
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Notes

Abstract

A discussion of historical lessons that RISC-V did learn from, and mistakes that it repeated. Focused on the design constraints forced by RVC and RVV, as well as the choices around breaking out the F and D profiles out from a mandatory vector unit, and the state changes that come with it.

The broad context will be specific to OoO SS processors

Speakers

FelixCLC

Perf & ASM nerd drifted off to ML side quests.

Care about clean specs, clean mandates, HPC, IEEE754 & the BLAS.

Eng at a startup, prev Weather @Canada

Helps with HPC.Social, occasional writer for Chips and Cheese

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