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FOSDEM PWA

RISC-V Extension Porting without the boring part

UD6.215 | Day 1 | 10:35 - 11:00 | Speakers: Afonso Oliveira

RISC-V Extension Porting without the boring part
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Abstract

RISC-V now spans 100+ extensions and over a thousand instructions. Binutils, QEMU, and other projects maintain separate instruction definitions, leading to duplication, mismatches, and slower support of new features.

UDB provides a machine-readable, validated source of truth covering most of the ISA. Our generator currently produces Binutils and QEMU definitions directly from UDB, cutting the effort for standard and custom extension bring-up. And with automated CI checks against current Binutils data, everything stays aligned as the ecosystem evolves.

In this talk, we’ll show how UDB enables new and custom extension by:

  • Automating part of of Binutils support
  • Allowing faster integration on other SW projects like QEMU

Speakers

Afonso Oliveira

I'm a SW engineer mostly working in RISC-V. I have experience in RISC-V HW enablement as part of my work on ARC-V processsors and I have also contributed to many RISC-V open-source projects, from software to the ISA Manual. I have also helped to create the RISC-V Unified DB -https://github.com/riscv-software-src/riscv-unified-db/.

Find me on github.com/afoliveira/

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