Open-Source CPU: Deep-dive into RISC-V CFU and Zephyr

Day 1 | 17:15 | 00:40 | H.1309 (Van Rijn) | Mohammed Billoo

Note: I'm reworking this at the moment, some things won't work.

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RISC-V's instruction set architecture (ISA) has enabled seasoned embedded software engineers to experiment with FPGAs since numerous open-source RISC-V cores can be flashed onto an FPGA.

The Zephyr Project is rapidly emerging as a leading real-time operating system (RTOS). Zephyr integrates open-source and security best practices to ensure a vendor-neutral, secure, and reliable platform.

One of the exciting features of the RISCV ISA is the Custom Function Unit (CFU), which enables a framework to support custom operations in hardware, which is accessible from software. In this talk, Mohammed will provide an in-depth demonstration on how to add a CFU into a RISCV core on an FPGA, how to make the appropriate calls from Zephyr, and the possibilities that the CFU enables for hardware acceleration in embedded systems.